1. Field of the Invention
The present invention relates to a synchronizing signal generator for use in an apparatus which detects a synchronizing signal of digital data.
2. Description of the Prior Art
Heretofore, digital data is comprised of sync. (synchronizing) pattern, data ID0 (ID number assigned to each of sync. blocks which will be described later on) and data ID1 (representing content of data) all of which are needed when digital data is reproduced. FIG. 1 of the accompanying drawings shows an arrangement of a conventional synchronizing signal generator for generating a synchronizing signal by detecting a sync. pattern of digital data, for example.
As shown in FIG. 1, digital data supplied from some suitable means, such as a reproducing system of a digital VTR (video tape recorder), not shown, or the like, is supplied to an input terminal 1. The digital data thus supplied to the input terminal 1 is supplied to a delay circuit 2, a variable shift register (VSR) 7 and a bit shift detector 6 which will be described later on. The delay circuit 2 delays the digital data supplied thereto through the input terminal 1 by a predetermined delay time L. Delayed data outputted from the delay circuit 2 is further delayed by a delay circuit 3 by a delay time 5L. A variable shift register (VSR) 4 latches therein output data Dx of the delay circuit 3 on the basis of a control signal supplied thereto from a bit shift phase corrector 16 which will be described later on. A latched output signal from the variable shift register 4 is supplied to some suitable means, such as the reproducing system of the digital VTR (not shown) or the like through an output terminal 5. The above predetermined delay time L has a duration corresponding to a length of one sync. block which will be described later on.
The bit shift detector 6 detects a bit shift amount of digital data D0 supplied thereto through the input terminal 1 on the basis of bit shift information contained in the sync. pattern which will be described later on. Detected shift amount data (referred to hereinafter simply as "signal" when necessary) PH0 representing a shift amount from the bit shift detector 6 is supplied to variable shift registers (VSRs) 7, 10 and the bit shift phase corrector 16 which will be described later on, respectively.
The variable shift register 7 bit-shifts the digital data D0 supplied thereto through the input terminal 1 on the basis of the shift amount data PH0 representing a shift amount from the bit shift detector 6. The variable shift register 10 bit-shifts digital data D1, delayed by the delay time L by the delay circuit 2, on the basis of the shift amount data PH0 representing a shift amount supplied thereto from the bit shift detector 6.
Shifted output data SD0, SD1 from the respective variable shift registers 7, 10 are supplied to sync/ID detectors 8, 11, respectively. The sync/ID detectors 8, 11 detect sync. patterns and ID data (ID0 and ID1) of the shifted output data SD0, SD1 supplied thereto from the variable shift registers 7, 10, i.e., the digital data supplied thereto through the input terminal 1 and the digital data D1 which results from delaying the digital data D0 by the delay time L by the delay circuit 2, and supply sync. patterns and ID data thus detected to a comparator 9.
The comparator 9 compares the sync. patterns and ID data supplied thereto from the sync/ID detectors 8, 11 and supplies a signal SY1 representing a compared result to a sync.position corrector 12. The sync. position corrector 12 supplies a correction signal for correcting a position of a synchronizing signal to the bit shift phase corrector 16 on the basis of the signal SY1 supplied thereto from the comparator 9 and the signal ID0 supplied thereto from the sync/ID detector 8. Also, the sync. position corrector 12 supplies a so-called inertia circuit 13 with a signal SYx. The inertia circuit 13 is what might be called a signal correcting circuit.
The bit shift phase corrector 16 generates a correction signal for effecting a bit shift on the basis of the signal SYx supplied thereto from the sync. position corrector 12 and supplies this correction signal to the variable shift register 4. Thus, the variable shift register 4 latches therein the digital data Dx supplied thereto from the delay circuit 3 and supplies the latched digital data Dx through the output terminal 5 to some suitable means, such as the reproducing system of the digital VTR (not shown) or the like.
The inertia circuit 13 generates a temporary synchronizing signal SYi on the basis of the signal SYx supplied thereto from the sync. position corrector 12, and supplies the temporary synchronizing signal SYi thus generated to a masking circuit 14. The masking circuit 14 masks temporary synchronizing signals SYi having a period shorter than the above predetermined delay time L and supplies other temporary synchronizing signal SYi through the output terminal 15 to some suitable means, such as the reproducing system of the digital VTR (not shown) or the like as a synchronizing signal SYm.
Inside circuit arrangements of the sync. position corrector 12 and the bit shift phase corrector 16 shown in FIG. 1 will be described below with reference to FIG. 2.
As shown in FIG. 2, the signal SY1 is supplied from the comparator 9 shown in FIG. 1 to an input terminal 50 as the compared output. The signal SY1 applied to the input terminal 50 is supplied to a sync. delay controller 55. The data ID0 is supplied to an input terminal 54 from the sync/ID detector 8 shown in FIG. 1.
The sync. delay controller 55 outputs signals LD0, LD1, LD2, LD3 and LD4 on the basis of the signal SY1 supplied thereto from the comparator 9 shown in FIG. 1 through the input terminal 50 and the signal ID0 supplied thereto from the sync/ID detector 8 shown in FIG. 1 through the input terminal 54. Relationship among the signals SY1, ID0 and signals LD0, LD1, LD2, LD3, LD4 outputted from the sync. delay controller 55 will be described below. When the signal SY1 is held at logic low "0" level, the signals LD0, LD1, LD2, LD3, LD4 are all held at logic low "0" level. When the signal SY1 is held at logic high "1" level, the signals LD0, LD1, LD2, LD3, LD4 are held at logic levels based on the values of the signal ID0, respectively. The sync. delay controller 55 includes a table for determining logic levels at which the signals LD0, LD1, LD2, LD3, LD4 are held in response to the logic level of the signal ID0.
Specifically, when the signal SY1 is held at logic high "1" level, the signals LD0, LD1, LD2, LD3, LD4 are held at the following logic levels in response to the values of the signal ID0 as shown on the table below:
TABLE ______________________________________ IDO LD0 LD1 LD2 LD3 LD4 ______________________________________ 1 1 0 0 0 0 2 1 1 0 0 0 3 1 1 1 0 0 4 1 1 1 1 0 5 1 1 1 1 1 X 1 0 0 0 0 ______________________________________
The signal LD0 is supplied to a delay circuit 56 and a delay circuit 68 in the bit shift phase corrector 16 which will be described later on. The signal LD0 delayed by the delay circuit 56 is supplied to an adder 57. The signal LD1 is supplied to the adder 57 and a delay circuit 69 in the bit shift phase corrector 16. The adder 57 adds the signal LD1 from the sync. delay controller 55 and the output from the delay circuit 56, i.e., signal which results from delaying the signal LD0, and supplies a signal SL1 representing an added result to a delay circuit 58.
The added output signal that was outputted from the adder 57 is delayed by the delay circuit 58 and then fed to an adder 59. The signal LD2 from the sync. delay controller 55 is supplied to the adder 59 and the bit shift phase corrector 16 which will be described later on. The adder 59 adds the signal LD2 from the sync. delay controller 55 and the delayed output from the delay circuit 58, i.e., the signal which results from delaying the signal provided by adding the signal LD1 to the delayed signal of the signal LD0, and supplies a signal SL2 representing an added result thereof to a delay circuit 60.
The delay circuit 60 delays the added output of the adder 59 and supplies a delayed output to an adder 61. The signal LD3 outputted from the sync. delay controller 55 is supplied to the adder 61 and the bit shift phase corrector 16 which will be described later on. The adder 61 adds the signal LD3 supplied thereto from the sync. delay controller 55 to the delayed output from the delay circuit 60, i.e., the signal which results from delaying the signal obtained when the signal LD2 is added to the signal obtained after the signal LD1 had been added to the delayed signal of the signal LD0. The adder 61 supplies a signal SL3 representing an added result thereof to a delay circuit 62.
The delay circuit 62 delays the added output from the adder 61 and supplies a delayed output to an adder 63. The signal LD4 outputted from the sync. delay controller 55 is supplied to the adder 63 and the bit shift phase corrector 16. The adder 63 adds the signal LD4 supplied thereto from the sync. delay controller 55 to the delayed output supplied thereto from the delay circuit 62, the i.e., signal which results from delaying the signal obtained when the signal LD3 is added to the signal obtained after the signal LD2 had been added to the delayed signal of the signal provided by adding the signal LD1 to the delayed signal of the signal LD0. The adder 63 then supplies a signal SL4 representing an added result thereof to a delay circuit 64 and the bit shift phase corrector 16 which will be described later on.
The delay circuit 64 obtains the signal SYx by delaying the signal SL4 supplied thereto from the adder 63, and supplies the signal SYx through a delay circuit 66, the bit shift phase corrector 16 and an output terminal 65 to the inertia circuit 13 shown in FIG. 1.
The delay circuit 68 in the bit shift phase corrector 16 obtains a delay signal PL0 by delaying the signal SL0 (the same as the signal LD0 in FIG. 2) supplied thereto from the sync. delay controller 55 on the basis of the shift amount data PH0 representing the shifted amount supplied thereto from the bit shift detector 6 shown in FIG. 1, and supplies the signal PL0 to a delay circuit 69. The delay circuit 69 receives the signal SL1 from the adder 57 as an enable signal and obtains a signal PL1 by delaying the signal PL0 supplied thereto from the delay circuit 68 on the basis of the shift amount data PH0 representing the shifted amount supplied thereto from the input terminal 67. Then, the delay circuit 69 supplies the signal PL1 to a delay circuit 70.
The delay circuit 70 receives the signal SL2 from the adder 59 as an enable signal and obtains a signal PL2 by delaying the signal PL1 supplied thereto from the delay circuit 69 on the basis of the shift amount data PH0 representing the shifted amount supplied thereto through the input terminal 67. Then, the delay circuit 70 supplies the signal PL2 to a delay circuit 71. The delay circuit 71 receives the signal SL3 from the adder 61 as an enable signal and obtains a signal PL3 by delaying the signal PL2 supplied thereto from the delay circuit 70 on the basis of the shift amount data PH0 representing the shifted amount supplied thereto through the input terminal 67. Then, the delay circuit 71 supplies the signal PL3 to a delay circuit 72.
The delay circuit 72 receives the signal SL4 from the adder 63 as an enable signal and obtains a signal PL4 by delaying the signal PL3 supplied thereto from the delay circuit 71 on the basis of the shift amount data PH0 representing the shifted amount supplied thereto through the input terminal 67. Then, the delay circuit 72 supplies the signal PL4 to a delay circuit 73. The delay circuit 73 obtains a signal PL5 by delaying the signal PL4 supplied thereto from the delay circuit 72 in response to the signal SL5 supplied thereto from the delay circuit 64 of the sync. position corrector 12 as an enable signal, and supplies the signal PL5 to a delay circuit 74. The delay circuit 74 receives the signal SL6 from the delay circuit 66 as an enable signal and obtains a signal PHL by delaying the signal PL5 supplied thereto from the delay circuit 73, and supplies the signal PHL through an output terminal 75 to the variable shift register (VSR) 4 shown in FIG. 1.
Inside circuit arrangements of the delay circuits 69, 70, 71, 72, 73 and 74 shown in FIG. 2 and inside circuit arrangements of the inertia circuit 13 and the masking circuit 14 will be described below with reference to FIGS. 3A, 3B and FIG. 4.
FIG. 3A shows inside circuit arrangements of the delay circuits 69, 70, 71 and 72 shown in FIG. 2. As shown in FIG. 3A, a signal LDIN (collectively refers to the signals LD0, LD1, LD2, LD3, LD4 supplied from the sync. delay controller 55 in FIG. 2) is supplied to an input terminal 100. A signal SLIN (collectively refers to the signals SL0, SL1, SL2, SL3, SL4 supplied from the sync. delay controller 55 and the adders 57, 59, 61, 63 in FIG. 2) is supplied to an input terminal 101. Shift amount data PH0 representing a shifted amount (shift amount data PH0 representing the shifted amount supplied through the input terminal 67 in FIG. 2) is supplied to an input terminal 102. A signal PIN (collectively refers to the signals PL0, PL1, PL2, PL3 and PL4 in FIG. 2) is supplied to an input terminal 103. Further, a clock signal is supplied to an input terminal 107 from some suitable means, such as a body circuit of the VTR (not shown) or the like. The signals PL0 through PL4 shown in FIG. 2 are outputted from an output terminal 108. The delay circuit 68 is formed of a flip-flop circuit.
In the delay circuits 69 through 72 shown in FIG. 3A, the input terminal 102 to which the shift amount data PH0 representing the shifted amount is connected to one fixed contact 104a of a switch 104, and the input terminal 103 is connected to the other fixed contact 104b of the switch 104. A movable contact 104c of the switch 104 is connected to the other fixed contact 105b of a switch 105, and one fixed contact 105a of the switch 105 is connected to a non-inverting output terminal Q of a flip-flop circuit 106. A movable contact 105c of the switch 105 is connected to a data input terminal D of the flip-flop circuit 106, and the input terminal 107 is connected to a clock input terminal of the flip-flop circuit 106. The non-inverting output terminal Q of the flip-flop circuit 106 is connected to the output terminal 108. Moreover, the signal LDIN (the signals LD0, LD1, LD2, LD3 and LD4 supplied from the sync. delay controller 55 in FIG. 2) is supplied from the input terminal 100 to control operation of the switch 104. The signal SLIN (the signals SL0, SL1, SL2, SL3 and SL4 supplied from the sync. delay controller 55 and the adders 57, 59, 61 and 63 in FIG. 2) is supplied from the input terminal 101 to control operation of the switch 105.
The switch 104 connects the movable contact 104c to one fixed contact 104a when the signal LDIN supplied thereto from the input terminal 100 is held at logic high "1" level to thereby select the shift amount data PH0 representing the shifted amount supplied thereto through the input terminal 102. The switch 105 connects the movable contact 105c to the other fixed contact 105b when the signal SLIN supplied thereto from the input terminal 101 is held at logic high "1" level to thereby select the signal supplied thereto from the switch 104.
FIG. 3B shows an inside circuit arrangement of the inertia circuit 13 shown in FIG. 1. As shown in FIG. 3B, the inertia circuit 13 comprises an input terminal 110 to which the signal SYx from the sync. position corrector 12 shown in FIGS. 1 and 2 is supplied, a counter 111 which is reset in response to the signal SYx supplied thereto through the input terminal 111, an AND circuit 112 which performs the logical AND of the signal SYx supplied thereto from the input terminal 110 and the output of the counter 111 and an output terminal 113 from which an output of the AND circuit 112 is supplied to the masking circuit 114 shown in FIG. 1.
The inertia circuit 13 resets the counter 111 when the signal SYx is supplied thereto through the input terminal 110, and obtains an ORed output of the counter and the signal SYx, to thereby obtain the temporary synchronizing signal SYi having the predetermined period L. Then, the inertia circuit 13 supplies the temporary synchronizing signal SYi through the output terminal 113 to the masking circuit 14 shown in FIG. 1.
FIG. 4 shows an inside circuit arrangement of the masking circuit 14 shown in FIG. 1. As shown in FIG. 4, the masking circuit 14 comprises an input terminal 115 to which there is supplied the temporary synchronizing signal SYi from the inertia circuit 13 shown in FIG. 1, a counter 116 which begins counting after having been reset by the temporary synchronizing signal SYi supplied thereto from the input terminal 115, a flip-flop circuit 117 which latches therein the output of the counter 116, an OR circuit 118, a flip-flop circuit 119 which performs the logical AND of the output from the counter 116 and the output of the flip-flop circuit 117 and which supplies the ANDed output to a control terminal of the counter 116, and an output terminal 120 (the output terminal 15 from which the synchronizing signal SYm is outputted in FIG. 1) from which the output of the flip-flop circuit 117 is outputted.
Operation of the masking circuit 14 shown in FIG. 4 will be described with reference to FIG. 5 of a timing chart.
In FIG. 5, reference symbol m1 depicts the temporary synchronizing signal SYi supplied to a reset terminal reset of the counter 116 from the input terminal 115 shown in FIG. 4, m2 depicts a carry signal outputted from the counter 116, m3 depicts a latched output outputted from the non-inverting output terminal Q of the flip-flop circuit 117, m4 depicts a latched output outputted from the non-inverting output terminal Q of the flip-flop circuit 119, and m5 depicts a latched output outputted from the inverting output terminal of the flip-flop circuit 119 and which is supplied to the control terminal of the counter 116.
The counter 116 is reset when the signal M1 supplied to the reset terminal reset thereof goes to logic high level, and stops the counting when the signal m5 supplied to the control terminal thereof goes to logic low "0" level. Then, the counter 116 increments the count value and counts the clock pulse during the (L-1) period when the signal m5 supplied to the control terminal thereof goes to logic high "1" level.
When the signal m1 supplied through the input terminal 115 to the reset terminal reset of the counter 116 goes to logic high "1" level, the counter 116 is reset. The counter 116 counts the clock pulse of the (L-1) period when the signal m5 supplied to the control terminal thereof goes to logic high "1" level. Then, the counter 116 outputs the carry signal m2 shown in FIG. 5 after having counted the clock pulses of the (L-1) period.
The carry signal m2 is supplied to the data input terminal D of the flip-flop circuit 117. The flip-flop circuit 117 latches therein the carry signal m2 supplied thereto from the counter 116 in response to a system clock (not shown). A latched output outputted from the flip-flop circuit 117 becomes the latched output m3 shown in FIG. 5. The latched output m3 is outputted through the output terminal 120 as a signal Syi.
The carry signal m2 from the counter 116 is on the other hand supplied to the OR circuit 118, and the OR circuit 118 performs the logical OR of the carry signal m2 and the signal m4 outputted from the non-inverting output terminal Q of the flip-flop circuit 119. When the carry signal m2 is held at logic high "1" level and the signal m4 is held at logic low level, the output of the OR circuit 118 goes to logic high "1" level. Therefore, when the signal m1 is held at logic low level in the next clock, the output developed at the non-inverting output terminal Q of the flip-flop circuit 119 goes to logic high "1" level, and the output developed at the inverting output terminal Q thereof goes to logic low "0" level, causing the counter 16 to be disabled. When, however, the signal ml of logic high "1" level is inputted thereto, the flip-flop circuit 119 is reset and the signal m5 goes to logic high "1" level, thereby energizing the counter 116.
The counter 116 is reset at the time the signal ml is held at logic high "1" level. Then, during the period in which the signal m5 is held at logic high "1" level, the counter 116 counts the clock pulses. When the counter 116 counts the clock pulses of the (L-1) period, the counter 116 outputs the carry signal m2.
In the example of FIG. 5, the fourth pulse from the left of the signal ml is masked by the masking circuit 14 shown in FIG. 1. Specifically, although the counter 116 is reset by the third pulse from the left of the signal ml and is energized to start counting, the counter 116 is reset by the fourth pulse from the left of the signal ml before counting the clock pulses of the (L-1) period. After the counter 116 was reset as described above, the counter 116 resumes the counting. When the counter 116 counts the clock pulses of the ( L-1) period, the counter 116 outputs the carry signal m2. According to the above-mentioned operation, the masking circuit 14 can mask the pulse having the period shorter than the (L-1) period.
An example of a format of the digital VTR will be described below with reference to FIGS. 6 and 7.
In FIG. 6, reference symbol SB depicts a format of one sync. block of the digital VTR. As shown in FIG. 6, one sync. block is comprised of sync. patterns SY0, SY1, ID data ID0, ID1, data D0, D1, . . . , D161 and inner parities P0, P1, . . . , P13. In this case, all elements except the sync. patterns SY0, SY1 constitute an inner code block.
FIG. 7 shows an example of the tape format of the digital VTR. As shown in FIG. 7, according to this example, one field is formed of six recording tracks (segments). Each segment is comprised of four audio sectors A1 through A4 provided at the center, servo tracking data S provided at the respective ends of the audio sectors A1 through A4 and video sectors V provided at the respective ends of the servo tracking data S. The audio sectors A1 through A4 are changed in arrangement at every two segments as shown in FIG. 7. Each sector is formed of a plurality of sync. blocks shown in FIG. 6.
Referring back to FIG. 6, the format of the sync. block of the digital VTR will be described below. FIG. 6 shows the ID data ID0 in correspondence with the sector arrangement shown in FIG. 7. The ID data ID0 represents the sync. block number having consecutive values to respective sync. blocks of the video sector V, the audio sectors A1 through A4 and the video sector V.
As shown in FIG. 6, the ID data ID is comprised of V/A representative of video sector or audio sector, TR representing a track number, SG representing a segment number, F representing a color frame and C/C representing a component signal or composite signal.
Continuity of data obtained when data is received will be described with reference to FIGS. 8A through 8D. In the following description, let it be assumed that ID in the digital data is decremented by "1" at every sync. pattern and that the sector has the same value within one block. Further, the sector is formed of video/audio data, track number data, two segment number data, two field number data and option flag data. Furthermore, since the data series is obtained by converting serial data into parallel data, bit must be shifted to the correct phase.
In FIGS. 8B through 8D, each of the hatched portions is comprised of sync. patterns (e.g., SYNC0, SYNC1), ID0, ID1 and data shown in FIG. 8A. ID0 and reference symbols L are shown in FIGS. 8B, 8C and 8D.
FIG. 8B shows the case that data is continuous upon reception. FIG. 8C shows the case that data is not continuous because the next data of the ID data ID+3 is lost when a tape is slackened or head is jumped. FIG. 8D shows the case that data is not continuous due to discontinuous point, such as a border of tracks of the VTR, a so-called edit gap produced as the border of video and audio recording areas or the like, for example.
When on the other hand a synchronizing signal is reproduced, a synchronizing error probability is increased as a byte error rate is deteriorated. Once the synchronizing signal is not reproduced, an error occurs at every synchronizing block, which further deteriorates the whole error rate. Specifically, when the byte error rate becomes deteriorated more than a synchronizing detection capability, error is increased in an avalanche fashion. Thus, it is to be noted that an error correction capability of the whole system depends upon the synchronizing detection capability rather than the error correction code capability. Therefore, considering balance between the synchronizing detection capability and the error correction code capability, it is to be noted that the high synchronizing detection capability should be provided as the byte error rate is deteriorated.
Operation of the conventional synchronizing signal generator shown in FIG. 1 will be described with reference to FIGS. 9A through 9H. In FIG. 9A, solid circles represent the case that the sync. pattern could be detected. In FIG. 9H, solid circles represent synchronizing signals obtained when the sync. pattern is detected continuously twice, and open circles represent synchronizing signals generated by the inertia circuit 13 and the masking circuit 14 shown in FIG. 1 when the sync. pattern is not detected continuously twice.
In the example shown in FIGS. 9A through 9H, it should be appreciated that a block in which the ID0 corresponds to "29" is dropped out.
When digital data shown in FIG. 9B is supplied, the sync. patterns shown by the solid circles in FIG. 9B are detected, and the detected sync. pattern shown in FIG. 9C is obtained. Then, the delay circuit 2 delays this detected sync. pattern by the delay time L and outputs the sync. pattern shown in FIG. 9D. The bit shift detector 6 obtains the shift amount data PH0 representing the shifted amount by detecting 5 bits from the digital data shown in FIG. 9B, and supplies the shift amount data PH0 representing the shifted amount to the variable shift registers 7, 10 and the bit shift phase corrector 16.
Digital data in which the sync. pattern is detected as shown in FIG. 9C is supplied to the variable shift register 7, and digital data in which the sync. pattern is detected as shown in FIG. 9D is supplied to the variable shift register 10.
The variable shift registers 7 and 10 bit-shift the digital data on the basis of the shift amount data PH0 representing the shifted amount supplied thereto from the bit shift detector 6 and supply the bit-shifted digital data to the sync/ID detectors 8 and 11. The sync/ID detectors 8 and 11 detect the sync. pattern and the ID data ID0, ID1 from the digital data supplied thereto from the variable shift registers 7, 10 and supply the sync. pattern and the data ID0, ID1 thus detected to the comparator 9.
The comparator 9 compares the sync. pattern and ID data ID0, ID1 supplied thereto from the sync/ID detectors 8 and 11, and supplies the signal SY1 representing the compared result to the sync. position corrector 12. Specifically, the output shown in FIG. 9E is obtained by performing the logical AND of the sync. pattern shown in FIG. 9C and the sync. pattern shown in FIG. 9D. The sync. patterns encircled by dashed lines in FIGS. 9C and 9D are obtained at the same timing point. More specifically, the sync. pattern in which the sync. pattern is continuously obtained twice can be detected by comparing the sync. pattern and ID data ID0, ID1 supplied thereto from the sync/ID detectors 8, 11 by the comparator 9.
The sync. position corrector 12 bit-shifts the digital data supplied thereto from the delay circuit 3 on the basis of the compared result shown in FIG. 9E. Also, the sync. position corrector 12 determines on the basis of the value of the ID data ID0 whether or not the sync. pattern is located at the starting portion of the block. If the sync. pattern is detected during the period from the starting portion of the block to six sync. blocks, then the sync. position corrector 12 delays the sync. pattern SYx. The delayed sync. pattern SYx is illustrated in FIG. 9F.
The reason that the sync. pattern SYx should be delayed will be described below. The reason that the sync. position corrector 12 delays the sync. pattern SYx on the basis of the compared result shown in FIG. 9E is to use a sync. pattern of a block delayed from a sync. pattern of a certain block of the data delayed by the delay time 6L by the delay circuits 2 and 3.
This reason will be described in another way again with reference to FIGS. 9A through 9H. Since the block in which the ID0 is "29" is dropped out as shown in FIG. 9A, in order to reproduce data by reliably obtaining a synchronizing signal from the block in which the ID0 is "28", the sync. pattern SYx should be delayed by the delay time L on the basis of the compared result SY1 obtained when the Sync. pattern is detected from the block in which the ID0 is "27" as shown in FIG. 9A.
The sync. pattern SYx shown in FIG. 9F is supplied to the inertia circuit 13. The inertia circuit 13 is locked to the sync. pattern SYx shown in FIGS. 9F and outputs the temporary synchronizing signal SYi shown in FIG. 9G. The temporary synchronizing signal SYi is supplied to the masking circuit 14. The masking circuit 14 masks a temporary synchronizing signal having an interval shorter than the delay time L from the temporary synchronizing signal SYi supplied thereto from the inertia circuit 13. The masking operation of the masking circuit 14 is illustrated in FIG. 9H. In FIG. 9H, solid circles represent synchronizing signals obtained from the detected sync. patterns, and open circles represent temporary synchronizing signals which are generated by the inertia circuit 13 in correspondence with sync. patterns that could not be detected. Study of FIG. 9 reveals that the masking circuit 14 masks the temporary synchronizing signal whose interval is shorter than the delay time L as encircled by dashed lines in FIG. 9G. The synchronizing signal from the masking circuit 14 is supplied through the output terminal 15 to some suitable means, such as the reproducing system of the digital VTR or the like.
On the other hand, the digital data is delayed by the delay circuit 3 by the delay time 5L, for example, and then supplied to the variable shift register 4, in which it is bit-shifted by the correction signal supplied thereto from the bit shift phase corrector 16 to thereby correct the phase thereof. Thereafter, digital data whose border (i.e., portion corresponding to the dropped data ID "29") is bit-shifted and returned equivalently to the correct position, thereby being supplied through the output terminal 5 to some suitable means, such as the reproducing system of the digital VTR (not shown) or the like. Therefore, the reproducing system of the digital VTR (not shown) reproduces digital data on the basis of the digital data supplied thereto from the output terminal 5 and the synchronizing signal SYm supplied thereto through the output terminal 15.
The conventional synchronizing signal generator shown in FIG. 1 determines that the sync. pattern is detected when two adjacent sync. patterns are both determined values, a relationship of data ID0 representing the synchronizing signal is represented by "+1" and also when the data ID1 representing the content of the data of the synchronizing block is the same. Then, the synchronizing signal generator locks the inertia circuit 13.
How the conventional synchronizing signal generator shown in FIG. 1 operates when two sync. patterns become erroneous will be described below with reference to FIGS. 10A through 10J.
FIG. 10A shows the values of ID0 similarly to FIG. 9A. FIGS. 10B, 10C and 10D show the case that the sync. pattern of the block number having the ID0 data value of "27" cannot be detected, FIGS. 10E, 10F and 10G show the case that the sync. patterns of blocks having the ID0 data values of "27", "26" cannot be detected, and FIGS. 10H, 10I and 10J show the case that the sync. patterns of blocks having ID data values of "27", "26" and "25" cannot be detected, respectively.
As shown in FIG. 10B, when the sync. pattern of the block having the ID0 value "27" cannot be detected, the comparator 9 determines that a block corresponding to "28" of the ID0 value and the adjacent block, i.e., the sync. pattern of the block having "27" of ID0 value, i.e., ID0 and ID1 are not coincident with each other. Thus, the comparator 9 outputs a compared output shown in FIG. 10C, and the inertia circuit 13 outputs the temporary synchronizing signal SYi shown in FIG. 10D. In FIG. 10D, solid circles represent detected sync. patterns, open circles represent synchronizing signals obtained from the sync. patterns generated by the inertia circuit 13, and "X" represent errors, i.e., the case that a synchronizing signal is not outputted.
As shown in FIG. 10E, when neither of the sync. patterns of the blocks in which the values of the ID0 are "27" and "26" are detected, the comparator 9 determines that the sync. pattern of block corresponding to "28" of the ID0 and two blocks adjacent to the former block, i.e., the sync. patterns of the blocks corresponding to "27" and "26" of the ID0, ID0 and ID1 are not coincident with each other. As s consequence, the comparator 9 outputs a compared output shown in FIG. 10F and the inertia circuit 13 outputs a synchronizing signal shown in FIG. 10G. In FIG. 10G, solid circles represent synchronizing signals obtained from detected sync. patterns, open circles represent synchronizing signals generated from the inertia circuit 13, and "X" represent errors, i.e,, the case that a synchronizing signal is not outputted.
As shown in FIG. 10H, when the sync. patterns of blocks in which values of ID0 are "27", "26" and "25" are not detected at all, the comparator 9 determines that the sync. pattern of the block corresponding to "28" of the ID0 value and the sync. patterns of three blocks adjacent to the former block, i.e., sync. patterns of blocks corresponding to "27", "26" and "25" of ID0 values, i.e., ID0 and ID1 are not coincident with each other. Consequently, the comparator 9 outputs a compared output shown in FIG. 10I and the inertia circuit 13 outputs a temporary synchronizing signal SYi shown in FIG. 10J. In FIG. 10J, solid circles represent synchronizing signals obtained from the sync. patterns that could be detected, open circles represent synchronizing signals generated from the inertia circuit 13 and "X" represent errors, i.e, the case that a synchronizing signal is not outputted.
In other words, when two sync. patterns or more become erroneous continuously, data provided in the interval that is not synchronized all become erroneous. As shown by the open circles in FIGS. 10D, 10G and 10J, once the synchronization is established, the synchronizing signal can be generated by the inertia circuit 13. It is the border of the block shown in FIG. 8D that causes a serious problems if the synchronization is not established.
The assignee of the present application has previously proposed a synchronizing signal extracting apparatus (see Japanese laid-open patent publication No. 60-137150). According to this previously-proposed synchronizing signal extracting apparatus, since a synchronizing output signal is obtained under the condition that synchronizing signals of the portions of incoming video signals are coincident with each other in timing and that address data are coincident with each other in content, it is possible to sufficiently reduce the probability in actual practice to the extent that a data portion of the same pattern as that of the synchronizing signal occurred at the time synchronizing signal data arrives will not be erroneously determined as the synchronizing signal.
Furthermore, the assignee of the present application has previously proposed a synchronizing signal detecting apparatus (see Japanese laid-open patent publication No. 1- 188132). According to this previously-proposed synchronizing signal detecting apparatus, incoming serial data is converted into parallel data, and a phase at which data pattern of a synchronizing signal is assumed to exist is detected from the parallel data. Then, the parallel data is shifted on the basis of the detected phase and a synchronizing signal is detected from the shifted data. Therefore, the synchronizing signal can be detected at lower speed and the circuit arrangement of this synchronizing signal detecting apparatus can be simplified.
Since, however, the above conventional synchronizing signal generator treats only the adjacent sync. patterns, a probability (sync. error rate) that the synchronizing signal cannot be detected is considerably large and cannot cope with the error correction capability.
The sync. error rate will be described below. A probability (byte error rate Psync) that 4 bytes of sync. pattern (SYNC2, ID1, SEC1) will cause an error is expressed by the following equation (1): EQU Psync=4.times.Pbyte (1)
where Pbyte represents the byte error rate.
Accordingly, when a signal is delayed by 6 sync. blocks and detected at the starting portion of the block, a probability that a synchronizing error will occur in the starting portion of the block, i.e., a synchronizing signal cannot be detected is expressed by the following equation (2): ##EQU1##
The byte error rate Pbyte=3.times.10.sup.-3. Also, assuming that the border of block, for example, occurs 1800 time per second, then a number Nb at which a synchronization is not established at the border of block is expressed by the following equation (3): ##EQU2##
This value of 1.3 (minutes) is a level which causes a serious problem in actual practice. Therefore, according to the conventional synchronizing signal generator of the system that treats only the adjacent sync. patterns, there is then the disadvantage that the probability of synchronizing error is considerably large.